1. general description the 74hc107-q100; 74hct107-q100 is a dual negative edge triggered jk flip-flop featuring individual j and k inputs, clock (cp ) and reset (r ) inputs and complementary q and q outputs. the reset is an asynchronous active low input and operates independently of the clock input. the j and k inputs control the state changes of the flip-flops as described in the mode select function table. the j and k inputs must be stable one set-up time prior to the high-to-low cloc k transition for predictable operation. inputs include clamp diodes that enable the use of cu rrent limiting resistors to interface inputs to voltages in excess of v cc . this product has been qualified to the automotive electronics council (aec) standard q100 (grade 1) and is suitable for use in automotive applications. 2. features and benefits ? automotive product qualif ication in accordance with aec-q100 (grade 1) ? specified from ? 40 ? c to +85 ? c and from ? 40 ? c to +125 ? c ? input levels: ? for 74hc107-q100: cmos level ? for 74hct107-q100: ttl level ? complies with jedec standard no. 7a ? esd protection: ? mil-std-883, method 3015 exceeds 2000 v ? hbm jesd22-a114f exceeds 2000 v ? mm jesd22-a115-a exceeds 200 v (c = 200 pf, r = 0 ? ) ? multiple package options 3. ordering information 74hc107-q100; 74hct107-q100 dual jk flip-flop with re set; negative-edge trigger rev. 1 ? 18 november 2013 product data sheet table 1. ordering information type number package temperature range name description version 74HC107D-Q100 ? 40 ? c to +125 ? c so14 plastic small outline package; 14 leads; body width 3.9 mm sot108-1 74hct107d-q100 74hc107pw-q100 ? 40 ? c to +125 ? c tssop14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm sot402-1
74hc_hct107_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 1 ? 18 november 2013 2 of 17 nxp semiconductors 74hc107-q100; 74hct107-q100 dual jk flip-flop with reset; negative-edge trigger 4. functional diagram fig 1. logic symbol fig 2. iec logic symbol d d d 4 4 4 - - 4 5 4 4 - & |